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| Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers A merged combination of bipolar and MOS technology gives these devices an interface flexibility beyond the reach of standard logic buffers and power driver arrays. Typical applications include driving multiplexed LED displays or incandescent lamps. The A6821 has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers. The CMOS inputs are compatible with standard CMOS logic levels. TTL circuits may require the use of appropriate pull-up resistors. By using the serial data output, the drivers can be cascaded for interface applications requiring additional drive lines. Package LW 16-pin Wide Body SOIC The A6821SA is furnished in a standard 16-pin plastic DIP. The A6821EA is a 16-pin plastic DIP, capable of operation from -40C to +85C. The A6821SLW is a 16-lead wide-body SOIC, for surfacemount applications. These devices are lead (Pb) free, with 100% matte tin plated leadframes. Package A 16-pin DIP FEATURES 3.3 V to 5 V logic supply range ABSOLUTE MAXIMUM RATINGS Output Voltage, VOUT .........................................50 V Logic Supply Voltage, VDD...................................7 V Input Voltage Range, VIN ..............-0.3 V to VDD +0.3 V Continuous Output Current (each output), IOUT ... 500 mA Package Power Dissipation, PD A6821SA/A6821EA..................................2.1 W A6821SLW............................................... 1.5 W Operating Temperature Range Ambient Temperature, TA ............-20C to +85C Storage Temperature, TS ..........-55C to +150C Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges. Power on reset (POR) To 10 MHz data input rate CMOS, TTL compatible -40C operation available Schmitt trigger inputs for improved noise immunity Low-power CMOS logic and latches High-voltage current-sink outputs Internal pull-up/pull down resistors APPLICATIONS Multiplexed LED displays Incandescent lamps Use the following complete part numbers when ordering: Part Number A6821SA-T A6821EA-T A6821SLW-T Package 16-pin DIP 16-pin DIP 16-pin wide body SOIC Ambient -20C to +85C -40C to +85C -20C to +85C Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Functional Block Diagram C LOC K S E R IAL DAT A IN LOG IC G R OUND V DD LOG IC S UP P LY S E R IAL DAT A OUT S T R OB E S E R IAL-P AR ALLE L S HIF T R E G IS T E R LAT C HE S OUT P UT E NAB LE (AC T IV E LOW) MOS B IP OLAR P OWE R G R OUND S UB OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 Typical Input Circuits VDD Typical Output Driver OUT STROBE OUTPUT ENABLE 7.2 k 3 k SUB VDD CLOCK SERIAL DATA IN www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25C, logic supply operating voltage Vdd = 3.0 V to 5.5 V Vdd = 3.3 V Characteristic Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Input Resistance Serial Data Output Voltage Maximum Clock Frequency2 Logic Supply Current Vdd = 5 V Typ. - - - - - - - 4.75 0.15 - - - - - - - - - 50 Symbol ICEX VCE(SAT) VIN(1) VIN(0) RIN VOUT(1) VOUT(0) fc IDD(1) IDD(0) tdis(BQ) ten(BQ) tp(STH-QL) tp(STH-QH) tf tr tp(CH-SQX) Test Conditions VOUT = 50 V IOUT = 100 mA IOUT = 200 mA IOUT = 350 mA Min. - - - - 2.2 - 50 Typ. - - - - - - - 3.05 0.15 - - - - - - - - - 50 Max. Min. 10 1.1 1.3 1.6 - 1.1 - - 0.3 - 2.0 100 1.0 1.0 1.0 1.0 1.0 1.0 - - - - - 3.3 - 50 4.5 - 10 - - - - - - - - - Max. 10 1.1 1.3 1.6 - 1.7 - - 0.3 - 2.0 100 1.0 1.0 1.0 1.0 1.0 1.0 - Units A V V V V V k V V MHz mA A s s s s s s ns IOUT = -200 A IOUT = 200 A One output on, OE = L, ST = H All outputs off, OE = H, ST = H, P1 through P8 = L VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF IOUT = 200 A 2.8 - 10 - - - - - - - - - Output Enable-to-Output Delay Strobe-to-Output Delay Output Fall Time Output Rise Time Clock-to-Serial Data Out Delay 1Positive (negative) current is defined as conventional current going into (coming out of) the specified device pin. 2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed. Truth Table Serial Data Clock Input Input H L X Shift Register Contents I1 H L I2 I3 ... I8 R7 R7 R8 X P8 Serial Data Output R7 R7 R8 X P8 L H R1 R2 R3 ... P1 P2 P3 ... X L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State OE = Output Enable ST = Strobe Latch Contents Strobe Input I1 I2 I3 ... I8 Output Enable Input Output Contents I1 I2 I3 ... I8 R1 R2 ... R1 R2 ... X X ... R1 R2 R3 ... X P1 P2 P3 ... R8 P8 X L H P 1 P2 P3 ... P8 H H H ... H X X ... www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) C CLOCK A SERIAL DATA IN DATA 50% B 50% t p(CH-SQX) SERIAL DATA OUT D STROBE 50% 50% DATA E OUTPUT ENABLE LOW = ALL OUTP UTS E NABLE D tp(STH-QH) tp(STH-QL) 90% OUT N DATA 10% HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D) OUTPUT ENABLE 50% t en(BQ) tr t dis(BQ) OUT N 10% tf 90% 50% DATA Key A B C D E Description Data Active Time Before Clock Pulse (Data Set-Up Time) Data Active Time After Clock Pulse (Data Hold Time) Clock Pulse Width Time Between Clock Activation and Strobe Strobe Pulse Width Symbol tsu(D) th(D) tw(CH) tsu(C) tw(STH) Time (ns) 25 25 50 100 50 NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Powering-on with the inputs in the low state ensures that the registers and latches power-on in the low state (POR). Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be high during serial data entry. When the OUTPUT ENABLE input is high, all of the output buffers are disabled (OFF). The information stored in the latches or shift register is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input low, the outputs are controlled by the state of their respective latches. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Maximum Allowable Duty Cycle, IOUT = 200 mA, VDD = 5 V Number of Outputs ON A6821SA/A6821EA 25C 90% 100% 100% 100% 100% 100% 100% 100% 67% 77% 90% 100% 100% 100% 100% 100% A mbient T emperature 40C 50C 60C 79% 90% 100% 100% 100% 100% 100% 100% 59% 68% 79% 95% 100% 100% 100% 100% 72% 82% 96% 100% 100% 100% 100% 100% 54% 62% 72% 86% 100% 100% 100% 100% 65% 74% 86% 100% 100% 100% 100% 100% 49% 56% 65% 78% 98% 100% 100% 100% 70C 57% 65% 76% 91% 100% 100% 100% 100% 43% 49% 57% 68% 86% 100% 100% 100% 8 7 6 5 4 3 2 1 A6821SLW 8 7 6 5 4 3 2 1 Terminal List Table Name CLK Description Clock Serial Data In Logic Ground* VDD ST OE SUB OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Logic Supply Serial Data Out Strobe Output Enable (active low) Power Ground* Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Serial Data Output Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 * There is an indeterminate resistance between logic ground and power ground. For proper operation, these terminals must be externally connected together. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 16-pin DIP Package LW 16-pin Wide Body SOIC CLOCK SERIAL DATA IN LOGIC GROUND LOGIC SUPPLY SERIAL DATA OUT STROBE OUTPUT ENABLE POWER GROUND 1 2 3 4 5 6 7 8 CLK 16 15 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 C LOC K S E R IAL DAT A IN LOG IC G R OUND LOG IC S UP P LY S E R IAL DAT A OUT S T R OB E OUT P UT E NAB LE P OWE R G R OUND 1 2 C LK 16 15 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 SHIFT REGISTER S HIF T R E G IS TE R 14 3 4 5 6 7 8 S UB ST OE V DD 14 LATCHES LAT C HE S VDD 13 12 11 10 9 13 12 11 10 9 ST OE SUB www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers Package A 16-pin DIP Dimensions in Inches (controlling dimensions) 16 9 0.014 0.008 0.430 0.280 0.240 MAX 0.300 BSC 1 0.070 0.045 0.100 0.775 0.735 BSC 8 0.005 MIN 0.210 MAX 0.015 MIN 0.150 0.115 0.022 0.014 Dwg. MA-001-16A in Dimensions in Millimeters (for reference only) 16 9 0.355 0.204 10.92 7.11 6.10 MAX 7.62 BSC 1 1.77 1.15 2.54 19.68 18.67 BSC 8 0.13 MIN 5.33 MAX 0.39 MIN 3.81 2.93 0.558 0.356 Dwg. MA-001-16A mm NOTES: 1. Lead thickness is measured at seating plane or below. 2. Lead spacing tolerance is non-cumulative. 3. Exact body and lead configuration at vendor's option within limits shown. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers 16-pin Wide Body SOIC Dimensions in Inches (for reference only) 16 9 0.0125 0.0091 Package LW 0.2992 0.2914 0.419 0.394 0.050 0.016 0.020 0.013 1 2 3 0.4133 0.3977 0.050 BSC 0 TO 8 0.0926 0.1043 0.0040 MIN. Dwg. MA-008-16A in Dimensions in Millimeters (controlling dimensions) 16 9 0.32 0.23 7.60 7.40 10.65 10.00 1.27 0.40 0.51 0.33 1 2 3 10.50 10.10 1.27 BSC 0 TO 8 2.65 2.35 0.10 MIN. Dwg. MA-008-16A mm NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor's option within limits shown. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 Data Sheet 26185.112B A6821 DABiC-5 8-Bit Serial Input Latched Sink Drivers The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c)2004, 2005 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 9 |
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